Semiconductor Production

In the production of semiconductors, advanced packaging technologies such as fan-out panel level packaging (FOPLP) make a decisive contribution to the development of high-performance, compact chips. We offer you the necessary production equipment and technological know-how.

Advanced Packaging Technologies as a Driver of Innovation

Driven by the rapid growth of high-end AI servers and advances in generative AI technologies, the semiconductor industry is faced with new requirements regarding multi-chip integrations with powerful GPUs, SoC designs and HBM. New, innovative and maximally efficient solutions and approaches are required.  

This is where our key technology comes into play - fan-out panel level packaging (FOPLP). With this approach, assembly takes place on a larger panel (compared to the conventionally used wafer). Multiple chips are processed on the panel at the same time, resulting in higher efficiency and cost savings. The chip has more connections distributed over a larger area, resulting in a higher packing density. This technology makes it possible to produce more powerful and compact chips with a higher I/O density.

Another advanced packaging technology for optimizing the integration and packaging of semiconductors is Chip-on-Panel-on-Substrate (CoPoS) technology. This also ensures optimized heat dissipation, higher I/O density and enables a more compact design.

RDL Redistribution Layers
FOPLP CoPos

Our “CoPoS” Chip-on-panel-on-substrate Technology

Our solutions utilize rectangular panel-like substrates instead of traditional round wafers. Materials include glass, organic, and stainless steel, offering process areas from 510 mm x 515 mm to 700 mm x 700 mm, currently the largest industrial dimension, with production capacity equivalent to approximately eight times that of 12-inch wafers. The CoPoS concept offers high manufacturing flexibility, enhanced production efficiency, and the ability to accommodate more stacked chips within a single IC package.

The RDL Process as an Integral Part of FOPLP

The increasing demand for advanced electronics is driving the technology of homogeneous or heterogeneous integration. By utilizing the RDL process, the latest multi-chip packaging trends are shifting from PCB or IC substrates to advanced integration technologies such as the thin film process or the 2.5D silicon interposer.

Panel Level Packaging RDL Solutions for Chip-first and Chip-last packaging Techniques

With our extensive process and technology expertise, we can provide customized RDL solutions for various metal layer interconnect structures and packaging forms. Our solution targets chip products including power management ICs, radio frequency ICs, smaller ICs manufactured by using the chip-first process and, AI chips manufactured by using chip-last packaging technology.

Their advantages:

  • Reduction of the package thickness
  • Strengthening the basis for homogeneous or heterogeneous integration
  • Simplification of the process flow and reduction of material costs

We Pave your Way Towards Mass Production

Thanks to our extensive technology portfolio, we can offer customized and highly efficient integrated manufacturing solutions for mass production. Our FOPLP RDL production solutions include the following building blocks and is suitable for various subtrates:

Vertical Electroplating: Novel Key Technology for Achieving Your Targets Within the RDL Process

The new vertical electroplating system does not require a stencil, which saves the purchase costs for the stencil, the consumption of electroplating solution and the costs for the cleaning solution during the process.

In addition, the electroplating system has a modular design and can be configured flexibly depending on the customer's production capacity and operating area. The components can be operated and dismantled quickly, are easy to maintain and can help the customer to run an efficient production.

Your benefits:

Plating ICs
  • Excellent plating uniformity: <10% for larger panels and small through holes (<25µm) can be filled
  • No gap formation for through holes or vias
  • Unique jig free design reduces chemical consumption and saves maintenance costs

Chip-on-Panel-on-Substrate (CoPoS) boots system integration through panel-level packaging

We are looking forward to your inquiry!

Contact us